 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| features ? pin-to-pin and register-to-register compatible with siemens 2186 ? full duplex 2b+d isdn s/t transceiver according to ccitt i.430 ? gci digital interface ? 3 types of 8-bit cpu interface ? receive timing recovery with adaptively switched thresholds ? e-channel monitoring pin configuration general descriptions mx97102 implements the 4-wire s/t interface used to link voice/data terminals to an isdn. it is designed for the user site of the isdn-basic access, two 64kbit/s b channels and a 16kbit/s d channel. mx97102 can be mainly divided into three portions ac- cording to their interfaces. except these three interface functions, it also provides the lapd controller which handles the hdlc packets of the isdn d-channel for the associated microprocessor. the first, s/t interface controller, provides all electrical and logical functions of the s/t interface, such as s/t transceiver, activation/deactivation, timing recovery, ? programmable sds1,sds2 ? d-channel access control ? lapd(hdlc) support with fifo(2x64) buffers ? activation/deactivation ? multiframing with s and q bit access ? cpu access to b and ic channels ? watchdog timer ? package types : p-lcc-44, p-lqfp-64 multiframe s and q channels, and d-channel access and priority control for communicating with remote equipments. the second is the microprocessor interface controller which offers the registers compatible with siemens psb2186, provides three types of microprocessor in- terface, such as motorola bus mode, intel multiplexed mode and intel non-multiplexed mode. the last portion is the gci interface controller which is used to connect different voice/data application mod- ules for local digital data exchangements. 1 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 isdn s/t controller 44-plcc 64-plqfp mx97102 psds1 psds2 prst pa5(eaw) vssd pdcl pfsc1 nc vssd echo pa 4 prdn(ds) pwrn(r/w) pcsn pale pidp1 pidp0 psx2 psx1 vdd nc nc pa 1 pa 2 pad7 pad6 pad5 pad4 pad3 pad2 pad1 pad0 pa 0 pa 3 nc nc vssd pbcl pintn vssa pxtal2 pxtal1 psr2 psr1 64440 39 34 29 7 12 17 18 23 28 1 mx97102 nc pa 2 pa 1 psds1 psds2 prst pa5(eaw) nc vssd pdcl pfsc1 nc vssd echo pa 4 pa 3 nc nc pa 0 prdn(d5) pwrn(r/w) pcsn pale pidp1 pidp0 psx2 psx1 vdd nc nc nc nc nc nc nc nc pad7 pad6 pad5 pad4 pad3 pad2 pad1 pad0 nc nc nc nc nc nc nc nc nc vssd pbcl pintn nc vssa pxtal2 pxtal1 nc psr2 nc psr1 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
2 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 block diagram multiframe control activation/ deactivation transmitter control and data interface signals gci interface receiver dpll echo up interface osc s/t interface lap-d pidp0 pidp1 pdcl pfsc1 figure 2: functional block diagram 7.68mhz b-channel switching fifo prst watch dog reset source pintn microprocessor interface 3 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 pin description (44-pin) table 1: mx97102 pin descriptions lqfp plcc pad# pad# pin name i/o description 37 41 pad0(d0) multiplexed bus mode:address/data bus from the cpu system to this devic 38 42 pad1(d1) ,and data between the cpu system and this device. 39 43 pad2(d2) non-multiplexed bus mode:data bus between the cpu system and this 40 44 pad3(d3) i/o device. 41 1 pad4(d4) 42 2 pad5(d5) 43 3 pad6(d6) 44 4 pad7(d7) 27 37 pcsn i chipselect:a logic "low" enable this device for a read/write operation. 28 38 pwrn(r/w) i read/write:a logic "high" indicates a valid read operation by cpu. a logic "low" indicates a valid write operation by cpu.(motorola bus mode) write:a logic "low" indicates a write operation.(intel bus mode) 29 39 prdn(ds) i data strobe: the rising edge marks the end of a valid read or write operation (motorola bus mode). read:a logic "low" indicates a read operation.(intel bus mode) 8 23 pintn open interrupt request:the signal is a logic "low" when this device requests an drain interrupt. it is an open drain output. 1~5, 14 nc 9,13,15 19,20 no used. 17~20 29,30 31~36 45~49 56,60 26 36 pale i address latch enable:a logic "high" indicates an address on the address/ data bus(multiplexed bus type only). ale also selects the micro-processor interface type (multiplexed or non-multiplexed). 54 9 prst i/o reset:a logic "high" on this input forces this device into reset state. the minimum pulse length is four dcl-clock periods or four ms. if the terminal specific functions are enabled,this device may also output a reset signal. 59 13 pfsc1 o(i) frame sync 1:frame sync output. logic "high" dur ing channel 0 on the gci interface. this pin becomes input if test mode is programmed (register adf1). 58 12 pdcl o(i) data cloc k:clock of frequency, 1536khz output, equals to twice the gci data rate. this pin becomes input if test mode is programmed (register adf1) 62 16 echo o this pin output the echo bit from the receiving line. 4 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 table 1: mx97102 pin descriptions(continued) lqfp plcc pad# pad# pin name i/o description (non-multiplexed bus mode) 30 40 pa0 i address bit 0 51 6 pa1 i address bit 1 50 5 pa2 i address bit 2 64 18 pa3 i address bit 3 63 17 pa4 i address bit 4 55 10 pa5(eaw) i address bit 5; external awake, when terminal specific function en abled, this pin is used as an external awake line. if a falling edge on this input is detected, it generates an interrupt and a reset pulse. 7 22 pbcl o bit clock:clock of frequency 768khz equal to the gci data rate. 52,53 7,8 psds1,2 o serial data strobe 1&2 : programmable strobe signals, selecting either one or two b or ic channels on gci interface, is supplied via this line. (registers adf2,4) 6,57,61 11, 15 21 vssd - digital ground 10 24 vssa - analog ground 21 31 vdd - power supply (5v 5%) 12 26 pxtal1 i connection for crystal or external clock input. 11 25 pxtal2 o connection for external crystal. left unconnected if external clock is used. 14 27 psr2 16 28 psr1 i s-bus receiver input 22 32 psx1 s-bus transmitter output(positive) 23 33 psx2 o s-bus transmitter output(negative) 24 34 pidp0(dd) gci-data port 0 (dd) 25 35 pidp1(du) i/o gci-data port 1 (du) open drain without internal pull-up resister or push-pull. absolute maximum ratings table 2: absolute maximum ratings rating value maximum supply voltage (vdd) 6v dc input voltage on any pin -0.4vto vdd+0.4v storage temperature range -55 c to 150 c operating free air temperature range 0 c to 70 c 5 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 dc characteristics table 3: dc characteristics temperature from 0 to 70 c; vdd = 5v 5%, vssa = 0v, vssd = 0v symbol parameter conditions min. value max. value unit remarks vil l-input voltage -0.4 0.8 v vih h-input voltage 2.0 vdd+0.4 v all pins except vol l-output voltage iol= 2ma 0.45 v psx1, psx2, vol1 l-output voltage (idp0) iol= 7ma 0.45 v psr1, psr2 voh h-output voltage ioh= -400ua 2.4 v voh h-output voltage ioh= -100ua vdd-0.75 v ili input leakage current 0 7 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 figure 3(c) multiplexed address timing in intel bus mode ad0-ad7 ale wr x cs or rd x cs tals taa tla tal tad address a0-a5 figure 3(d) non-multiplexed address timing in intel bus mode wr x cs or rd x cs tah tas address motorola bus mode figure 4(a) microprocessor read timing in motorola bus mode d0-d7 ale cs x ds trwd tdsd tri tdf trr trd data 8 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 ad0-ad5 figure 4(c) non-multiplexed address timing in motorola bus mode cs x ds tah tas address table 6: parameters for microprocessor interface timing parameter symbol limit value unit min. max. ale pulse witdh taa 40 ns address setup time to ale tal 10 ns address hold time to ale tla 10 ns address latch setup time to wr, rd tals 0 ns address setup time tas 10 ns address hold time tah 10 ns ale guard time tad 15 ns ds delay after rw setup tdsd 0 ns rd pulse width trr 50 ns data ouput delay from rd trd 50 ns data float from rd tdf 52 ns rd control interval tri 50 ns w pulse width tww 50 ns data setup time to w, cs tdw 10 ns data hold time from w, cs twd 10 ns w control interval twi 50 ns figure 4(b) microprocessor write timing in motorola bus mode d0-d7 r/w cs x ds tdsd twi twd tww tdw data 9 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 isdn access architecture mx97102 is designed especially for subscriber termi- nal equipment with s/t interfaces, four wire, two pairs for transmission and receiption separately, are con- nected to the nt equipment at the user site. via the nt equipment, subscribers could dial up to the wide-area network with the traditional telephone line. the nt serves a converter between the u interface at the ex- te(1) telephone line isdn central office lt- s lt- t t u s pbx(nt2) nt1 lt lt nt1 where - te is an isdn terminal - lt-s is a subscriber line termination - lt-t is a trunk line termination - lt is a trunk line termination in the central office lt- s lt- s direct subscriber access figure 5 : isdn - basic subscriber access achitecture te(8) te(1) te(1) te(8) s s = mx97102 change and the s interface at the user premises. the nt may be either an nt1 only or an nt1 together with an nt2 connected via the t interface which is physi- cally identical to the s interface. nt2 may include higher level functions like multiplexing and switching as in a pbx. figure 5 illustrates the connections between the user site to the public domain of central office. mx97102 is based on the isdn basic access, 192kbit/ s, which consists of two circuit-switched 64 kbit/s b channels and a message oriented 16kbit/s d channel for packetized data, signaling and telemetry informa- tion. the d channel is processed by the lapd control- ler contained in the mx97102 and routed via a parallel cpu interface to the terminal processor. the high level support of the lapd protocol which is implemented by the mx97102 allows the use of a low cost processor in cost sensitive applications. functional and operational description 10 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 gci connection with the gci interface, mx97102 could connect differ- ent voice/data (v/d) application modules. up to eight d-channel components may be connected to the d and c/i (command/indication) channels (tic-bus). tic-bus arbitration is also implemented in mx97102. data transfers between the mx97102 and the v/d mod- ules are done with the help of the gci monitor chan- nel protocol. each v/d module can be accessed by an individual address. two intercommunication channels ic1 and ic2 allow a 2*64kbit/s transfer rate between voice/data modules. figure 6 shows one gci connec- tion, data module a uses d-channel for data transfer, a voice processor is connected to a programmable digi- tal processing codec filter via ic1 and a data encryp- tion module to a data device via ic2. meanwhile, b1 is used for voice communication, b2 for data communi- cation. mx97102 d, c/i microprocessor data module a data module b1 speech processing speech modules figure 6: examples of gci connection dsp codec module b1 data encryption data modules data module b gci functions in terminal applications, the gci constitutes a powerful backplane bus offering intercommunication and sophisti- cated control capabilities for peripheral modules. gci frame is composed of three channels ( see figure 6-1 below): - channel 0 contains 144kbit/s (for 2b+d) plus monitor and command/indication channels for the layer-1 device. - channel 1 contains two 64kbit/s intercommunication channels plus monitor and command/indication channels for other gci devices. - channel 2 is used for gci-bus arbitration. only the command/indication are used in channel 2. 11 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 the gci interface is operated in the open dr ain mode in order to takes advantage of the bus capability. in this case pull-up resisters (1kohm-5kohm) are required on pidp0 and pidp1. gci off function in gci terminal mode (spcr:spm=0) the gci inter- face can be switched off for external devices via iof bit in adf1 register. if iof=1, the interface is switched off. thus, dcl, fsc1, idp0/1 and bcl are high impedence. gci direction control for test applications, the direction of idp0 (dd) and idp1 (du) can be reversed during certain time-slots within the gci frame. this is performed via the idc bit in the sqxr register. for normal operation sqxr:idc should be set to 0. figure 6-1 frame structure of gci gci has the 12-byte frame structure consisting of chan- nels 0, 1 and 2. (see figure 6-1 above) - idp0 carries the 2b+d channels from the s/t inter- face, and the monitor 0 and c/i 0 channels coming from the s/t controller; - idp1 carries the monitor 0 and c/i 0 channels to the layer-1. channel 1 of gci interface is used for internal commu- nication in terminal applications. two cases have to be distinguished, according to whether the mx97102 is op- erated as a master device or as a slave device. b1 fsc1 sds1 ipd0 (dd) ipd1 (du) b2 mono ch0 ch1 ch2 125 us d cio mr mx mr mx s/g bac tad a/b mr mx ic1 ic2 mon1 ci1 mr mx b1 idp0,1:768 kbit/s dcl :1536 khz fsc1 :8 khz bcl :768 khz bit clock sds1 :8khz programmable data strobe signal for selecting one or both b/ic channel(s) b2 mono d cio ic1 ic2 mon1 ci1 12 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 if idc is set to "0" (master mode): - idp0 carries the monitor 1 and c/i 1 channels as output to peripheral (voice/data) devices; - idp0 also carries the ic channels as output to other devices, if programmed (cxc1-0=01 in register spcr). if idc is set to "1" (slave mode): - idp1 carries the monitor 1 and c/i 1 channels as output to a master device; - idp0 carries the ic channels as output to other devices, if if programmed (cxc1-0=01 in register spcr). figure 6-2shows the connection in a multifunctional terminal with the mx97102 as a master and a voice/data module as a slave device. if gci-0 of mode register is programmed, bit 5 of the last byte in channel 2 on idp0 can be used to indicate the s-bus state (stop/go bit) and bit 2 to 5 of the last byte are used for tic-bus access arbitration. figure 6-2 gci port connection and data direction idp1 dd du voice/data module as slave idp0 gci interface idp0 idp1 mon1, c/i1, ic1, ic2 2b+d, c/i0, s/g, tic idp1 layer2 mx97102 as master s/t interface idp0 idp0 idp1 layer1 13 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 microprocessor access to b and ic channels the microprocessor can access the b and ic channels at the gci interface by reading the b1cr/b2cr or by reading and writing the c1r/c2r registers. furthermore it is possible to loop back the b channels from/to the s/ t interface or to loop back the ic channels from/to the gci interface without cpu intervention. note: x=1 for channel 1 or x=2 for channel 2 if the b-channel access is used for transferring 64kbit/ s voice/data information directly from the cpu port to the isdn s/t interface, the access can be synchro- nized to the gci interface by means of a synchronous transfer interrupt programmed in the stcr register. the general sequence of operations to access the b/ ic channels is: 1. program synchronous interrupt (st0) which causes the device to generate an sin interrupt at the begin- ning of an gci frame. 2. read or write register (bxcr, cxr) 3. set sc0 bit in the stcr to acknowledge sin inter- rupt. repeat this sequence from 1 to 3. cxc1 cxc0 cxr read cxr write bxcr read output to gci applications 0 0 icx - bx - bx, icx monitoring 0 1 icx icx bx icx bx monitoring, icx looping from/to gci 1 0 - bx bx bx bx access from/to s; transmission of a constant value in bx channel to s 1 1 bx bx - bx bx looping from s; transmission of a variable pattern in bx channels to s table 7-1 cpu access to b/ic channels by spcr register same procedure could be used at st1 and sc1 bits in the stcr register. the only difference is st1 gener- ates an sin interrupt at the middle of an gci frame instead of at the beginning. when cpu accesses b channels, we can set the iof bit to switch off the gci function. thus, external b-chan- nel sources (voice/data modules) can not disturb the b-channel access on the gci interface. four different functions are selected by the bits cxc1 and cxc0 in the spcr register. moreover, each chan- nel, b channel 0/1 and ic channel 0/1, is programmed individually. table7-1 shows the configurations. 14 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 figure 6-3(a) spcr : (cxc1, cxc0) = (0,0) bx and icx monitoring layer-1 functions bxcr bx icx idp0 (dd) fsc up b1 s/t interface cxr idp0(dd) gci interface idp1(du) b1cr c1r sco=1 st0 c2r b2cr b2 b1 b2 ic1 ic2 ic1 ic2 idp1 (du) b1 b2 b1 b2 ic1 ic2 ic1 ic2 15 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 figure 6-3(b) spcr : (cxc1, cxc0) = (0,0) bx and icx monitoring, icx looping (sqxr : idc = 0) layer-1 functions bxcr bx icx idp0 (dd) fsc up b1 s/t interface cxr idp0(dd) gci interface idp1(du) b1cr c1r sco=1 st0 c2r b2cr b2 b1 b2 ic1 ic2 ic1 ic2 idp1 (du) b1 b2 b1 b2 ic1 ic2 ic1 ic2 16 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 figure 6-3(c) spcr : (cxc1, cxc0) = (1,0) bx access from/to s/t transmission of constant value of s/t layer-1 functions bxcr bx bx idp0 (dd) fsc up b1 s/t interface cxr idp0(dd) gci interface idp1(du) b1cr c1r sco=1 st0 c2r b2cr b2 b1 b2 ic1 ic2 ic1 ic2 idp1 (du) b1 b2 b1 b2 ic1 ic2 ic1 ic2 17 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 figure 6-3(c) spcr : (cxc1, cxc0) = (1,1) bx looping from/to s/t transmission of variable pattern of s/t layer-1 functions cxr bx bx idp0 (dd) fsc up b1 s/t interface idp0(dd) gci interface idp1(du) b1cr sco=1 st0 b2cr b2 b1 b2 ic1 ic2 ic1 ic2 idp1 (du) b1 b2 b1 b2 ic1 ic2 ic1 ic2 18 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 monitor channel handling the monitor channel protocol is a handshake proto- col used for high speed information exchange between the mx97102 and other devices. the usage of the monitor channel protocol (see fig- ure 6-4 below): - for programming and controlling devices attached to the gci. examples of such devices are layer-1 trans- ceivers (using monitor channel 0), and peripheral v/ d modules that do not need a parallel microcontroller interface (by using monitor channel 1), such as the audio ringing codec filter. - for data exchange between two microcontroller sys- tems attached to two different devices on one gci backplane. use of the monitor channel avoids the necessity of a dedicated serial communication path be- tween the two systems. this simplifies the system de- sign of terminal equipments. note: mx97102 does not support the monitor chan- nel 0 operation. the implemented monitor handler can however be used with external layer-1 transceivers in case only the icc part of this device is used (adf1: tem, pfs). figure 6-4 monitor channel applications in gci interface the monitor channel operates on an asynchronous basis. while data transfers on the bus take place synchro- nized to frame sync, the flow of data is controlled by a handshake procedure using the monitor channel receive (mr0 or mr1) and monitor channel transmit (mx0 or mx1) bits. for example: data is placed onto the moni- tor channel and the mx bit is activated. the data will be transmitted repeatedly once per 8khz frame until the transfer is acknowledge via the mr bit. v/d module data communication (monitor1) control (monitor1) cpu v/d module mx97102 cpu 19 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 the microprocessor may either enforce a "1" in mr, mx by setting the control bit mrc1, mrc0 or mxc1, mxc0 of the mocr register to logic 0, or enable the control of these bits internally by the mx97102 accord- ing to the monitor channel protocol. thus, before a data exchange can begin, the control bit mrc(1,0) or mxc(1,0) should be set to "1" by the microprocessor. monitor handshake procedure - idle the mx and mr pair being held inactive for two or more frames constitutes the channel being idle in that direction. - start of transmission before starting a transmission, the cpu should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. this is in- dicated by a "0" in the monitor channel active (mac) status bit. after having written the monitor data transmit (mox) register, the microprocessor sets the monitor transmit control bit (mxc) to "1". this en- ables the mx bit to go active (0), indicating the pres- ence of valid monitor data (contents of mox) in the corresponding frame and remains active until an inac- tive-to-active transition (mda) of mr is received, indi- cating the receiver has read the data off the bus. as a result, the receiving device stores the monitor byte in its monitor receive register (mor) and gener- ates an mdr interrupt status. there are two different cases, general case and maxi- mum speed case, of the monitor handshake proto- col. bit max0(1) in the adf3 register is set to "1" for selecting the maximum speed case of monitor 0(1). * as a general case (max=0): the next byte is placed on the bus after the inactive to active transmission of mr as early as the next frame ( there is no limit to the maximum number of frames). at the time that the second byte is transmit- ted, mx is returned inactive for one frame time (mx inactive for more than one frame time indicates an end of message). in response to mx going active, mr will be deactivated for one frame time (the mx inactive to mr inactive delay can be any number of frame times) after mor is read. this procedure is repeated for each additional byte. (see figure6-5) figure 6-5 timing chart of general case transmitter receiver mx mox=1st mox=2nd mxe=1 mxc=1 mac=1 rd mor mda 1st byte mr rd mor rd mor mac=0 mda mda eom mox=nth mxc=0 2nd byte nth byte 125us mrc=0 mer mdr mdr mdr 20 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 as a maximum speed case (max=1): the transmitter can be designed for a higher data throughput than is provided by the general case described above. the transmitter can deactivate mx and transmit new data one frame time after mr is de- activated. in this way, the transmitter is anticipating that - first byte reception at the time the receiver sees the the first byte, indicated by the inactive-to-active transition of mx (mdr), mr is by definition inactive. in response to the activation of mx, microprocessor reads the monitor receive (mor) register. when it is ready to accept data (e.g. based on the value in mor, which in a point-to- multipoint application might be the address of the destinating device), it sets the mr contol bit (mrc) to "1" to enable the receiver to store succeeding moni- tor channel bytes and acknowledge them according to the monitor channel protocol. in addition, it en- ables other monitor channel interrupts by setting monitor interrupt enable (mre) to "1". - subsequent reception data is received from the bus on each falling edge of mx, and a mdr is generated. note that the data may actually be valid at the time that mx went inactive, one frame time prior to going active. mr is deactivated after the data is read and reactivated one frame time later. the transmitter will detect mr going inactive and anticipate its reactivation one frame time later. the transmission of the next data byte will begin at the same time that mr is going active. mr will be reactivated one frame time after it is deacti- vated, minimizing the delay between bytes (see figure 6-6). note that mr being held inactive for two or more frame times indicates an abort is being signaled by the receiver. figure 6-6 timing chart of maximum speed case this "mda interrupt - write data - mdr inter- rupt - read data - mda interrupt" handshake is repeated as long as the transmitter has data to send. -end of transmission (eom) when the last byte has been acknowledged by the receiver, the microprocessor sets the monitor transmit control bit (mxc) to "0". this enforces an in- active "1" state in the mx bit. two frames of mx inac- tive signifies the end of a message. thus, a monitor channel end of receiption (mer) interrupt status is generated by the receiver when the mx bit is received in the inactive state in two consecutive frames. as a result, the microprocessor sets the mrc to 0, which in turn enforces an inactive state in the mr bit. this marks the end of the transmission, making the monitor channel active (mac) bit return to 0. - abort during a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive mr bit value in two consecutive frames. this is effected by the microprocessor writing the mrc bit to "0". an aborted transmission is indi- cated by a monitor channel data abort (mab) in- terrupt status at the transmitter. transmitter receiver mx 1st byte * transmitter anticipates the falling edge of the receiver's acknowledgment *signals from/to cpu are the same with general case(figure6-8) mr 2nd byte nth byte eom 125us 21 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 c/i-channel handling & tic-bus access the command/indication channel carries real-time sta- tus information between the mx97102 and another de- vice connected to the gci. - one c/i channel (called c/i 0) conveys the commands and indications between the layer-1 and the layer-2 parts of the mx97102. it can be accessed by an external layer-2 device e.g. to control the layer-1 activation/de- activation procedures. c/i 0 channel access may be arbitrated via the tic bus access protocol. in this case the arbitration is done in c/i channel 2. the c/i 0 code is four bits long, could be read from cir0 (layer-1 to layer-2) and write to cix0 (layer-2 to layer-1). in the receive direction, the code from layer-1 is con- tinuously monitored, with an interrupt being generated any time a change occurs (cisq). a new code must be found in two consecutive gci frames to be considered valid and to trigger a c/i code change interrupt status (double last look criterion). - a second c/i channel (called c/i 1) can be used to convey real time status information between the mx97102 and various non-layer-1 peripheral devices such as arcofi. the channel consists of six bits in each direction. the c/i 1 channel is accessed via registers cir1 and cix1. a change in the received c/i 1 code is indicated by an interrupt status without double last look criterion. the tic-bus arbitration mechanism implemented in the last octet of gci channel 2 of the gci allows the ac- cess of external communication controller (up to 7) to the layer-1 functions provided in the mx97102 and to the d channel. to this effect the outputs of the control- lers are wired-and connected to pin idp1. the inputs of the iccs are connected to pin idp0. external pull-up resistors on idp0/1 are required. the arbitration mecha- nism must be activated by setting mode: dim2-0=001. an access request to the tic bus may either be gener- ated by software (cpu access to the c/i channel) or by the mx97102 itself (transmission of an hdlc frame). a software access request to the bus is effected by setting the bac bit (cix0 register) to 1. in the case of an access request, the mx97102 checks the bus accessed-bit (bit 5 of idp1 last octet of ch2, see figure6-1) for the status bus free, which is indi- cated by a logical 1. if the bus is free, the mx97102 transmits its individual tic-bus address programmed in the stcr register. the tic bus is occupied by the device which sends is address error-free. if more than one device attempt to seize the bus simultaneously, the one with the lowest address value wins. when the tic bus is seized by the mx97102, the bac- bit on idp1 is 0 until the access request is withdrawn. after a successful bus access, the mx97102 is auto- matically set into lower priority class, that is, a new bus access cannot be performed until the status bus free is indicated in two successive frames. if none of the devices connected to the gci interface request access to the d and c/i channels, the tic-bus address 7 will be present. the device with this address will therefore have access, by default, to the d and c/i channels. the availability of the s/t interface d chan- nel is indicated in bit5 stop/go (s/g=1: stop, s/g=0: go) of the idp0 last octet of c/i channel (figure6-1). 22 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 the receiver is designed as a threshold detector with adaptively switched threshold levels. pin psr1 delivers 2.5v as an output, which is the virtual ground of the input signal on pin psr2. the detector controls the switching of the receiver between two sensitivity levels (see figure6-8). figure 6-8 state diagram of the adaptive receiver - pre-filter compensation to compensate for the extra delay introduced into the received signal by a filter, the sampling of the receive signal can be delayed by programming bits tem and pfs in the adf1 register as shown below. tem pfs 0 0 no delay 0 1 delay 650ns 1 1 advance 390ns 1 0 test mode +5v vdd 2 : 1 psx1 psx2 psr1 psr2 mx97102 transmit pair protection circuits vssd vssa gnd 10uf figure 6-7: mx97102 external s-interface circuitry 2 : 1 receive pair yy yy z z {{ | logical 1 logical 0 logical 0 state 1 high sensitivity with vtr1=+225mv v sr2- v sr1 +225mv 0v -225mv y y zz zz { || state 2 |vmax| > 1v in two consecutive frames 750mv<|vmax|<1v 750mv<|vmax|<1v vmax<750mv or vmax>750mv vtr1, vtr2:threshold voltages of the receiver threshold detector vmax:maximum value of vsr2-vsr1 during one frame low sensitivity with vtr2=+375mv v sr2- v sr1 +375mv 0v -375mv 1 2 s/t interface line transceiver functions for the s/y interface follow the electrical specifications of ccitt i.430. according to this standard, pseudo-ternary encoding with 100% pulse width is used on the s/t interface. for both receive and transmit direction, a 2:1 transformer is used to connect the mx97102 transceiver to the 4 wire s/t interface. 23 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 activation/deactivation an incorporated finite state machine controls isdn layer-1 activation/deactivation according to ccitt i.430. fig- ure6-9 shows the state diagrams. table7-2 and table7-3 indicate the command and indication code descriptions. figure 6-9(a) state diagram x : unconditional command (arl, rs, ssz, scz) rsyd f5 unsynchron. i0 i0 i0 i0 i0 did diu f3 power down i0 i0 i0 ind. cmd. state ix ir pu aru f4 pend. act. i1 pu tim f3 power up i0 i0 dr aru f3 pend. deact. i0 i0 i0 aid aru f7 activated f8 lost frame i3 i3 i4 i4 i4 i4 i2 i2 i2 i2 ard rsyd f6 synchron. out in iom2 s rst tim i0 i0 i0 i0 i0 i0 x x x x i0 aru diu diu aru diu tim i0.diu tim tim x x uncond. states , 24 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 command (upstream) abbr. code reamrks timing tim 0000 activation of all output clocks is requested reset rs 0001 (x) send continuous zeros scz 0100 transmission of pseudo-ternary pulses at 96khz frequency (x) send single zeros ssz 0010 transmission of pseudo-ternary pulses at 2khz (x) activate request ar8 1000 activation command, set d-channel priority to 8 set priority 8 activate request ar10 1001 activation command, set d-channel priority to 10 set priority 10 activate request loop arl 1010 activation of test loop 3 (x) deactivate indication diu 1111 gci-interface clocks can be disabled upstream table 7-2 c/i command code descriptions figure 6-9(b) state diagram : unconditional transitions pu arl arl loop 3 closed i3 i3 i3 x * ti scz scz test mode continuous pulse ic * ei is:single pulse, 4khz ic:test pulse, 96khz x:forcing commands rs rs reset state i0 * i0 x ti at i arl loop 3 act. i3 x i0/ tis ssz ssz test mode single pulse is * x x 25 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 note: when in the activated state (ai8/ai10) the 2b+d channels are only transferred from the gci to the s/t interface if an activ ate request command is written to the cix0 register. level detection power down in power down state, only an analog level detector is active. all clocks, including the gci interface, are stopped. the data lines are "high" whereas the clocks are "low". an activation initiated from the exchange side (info2 in s bus detected) will have the consequence that a clock signal is provided automatically. from the terminal side an activation must be started by setting and resetting the spu bit in the spcr register. indication abbr. code reamrks power up pu 0111 gci clocking is provided deactivate request dr 0000 deactivation request by s interface error indication ei 0110 either : (pin prst = 1 and bit cfs = 0) or rs level detected rsyd 0100 signal received, receiver not synchronous activate request ard 1000 info 2 received downstream test indication ti 1010 test loop 3 activated or continuous zeros transmitted awake test indication ati 1011 level detected during test loop activate indication ai8 1100 info 4 received, d-channel priority is 8 or 9 with priority class 8 activate indication aii0 1101 info 4 received, d-channel priority is 10 or 11 deactivate indication did 1111 clocks will be disabled in mx97102, quiescent state downstream single zero transmitted tis 0101 send single zeros at 2khz frequency table 7-3 c/i command code descriptions 26 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 d-channel access the d-channel access procedure according to ccitt i.430 including priority management is fully implemented in the mx97102. by programmed the dim2-0 (mode register) to 001 or 011, stop/go bit is evaluated for d- channel access handling, that is, a collision is detected if the corresponding echo-bit value is different from the transmitted d-bit value. when this occurs, d-channel transmission is immediately stopped, and the echo channel is monitored to enable a subsequent d-chan- nel access to be attempted. the priority class (priority 8 or priority 10) is selected by transferring the appropriate activation command via the command/indication (c/i) channel of the gci inter- face to the layer-1 controller. 6.3.10 s- and q- channel access access to the received/transmitted s- or q- channel is provided via registers. as specified by ccitt i.430, the q bit is transmited from te to nt in the position normally occupied by the auxiliary framing bit (fa) in one frame out of 5, whereas the s bit is transmitted from nt to te in a spare bit (s). the functions provided by the mx97102 are: - synchronization to the received 20 frame multiframe by means of the received m bit pattern. synchronism is achieved when the m bit has been correctly received during 20 consecutive frames starting from frame num- ber 1 (table7-4). - when synchronism is achieved, the four received s bits in frames 1, 6, 11, 16 are stored as sqr1 to sqr4 in the sqrr register if the complete m bit multiframe pattern was correctly received in the corresponding multiframe. a change in any of the received four bits is indicated by an interrupt (cisq in ista and sqc in cir0). - when an m bit is observed to have a value different from that expected, the synchronism is considered lost. the sqr bits are not updated until synchronism is re- gained. the synchronization state is constantly indicated by the syn bit in the sqrr register. - when synchronism with the received multiframe is achieved, the four bits sqx1 to sqx4 stored in the sqxr register are transmitted ad the four q bit (fa-bit position) in frames 1, 6, 11, 16 respectively (starting from frame number one). otherwise the bit transmitted a mirror of the received fa-bit. at loss of synchronism (mismatch in m bit) the mirroring is resumed starting with the next fa-bit. - the s/t multiframe synchronization can be dis- abled in the star register (mult bit). 27 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 table 7-4 s- and q-channel structure frame number nt-to-te fa-bit position nt-to-te m bit nt-to-te s bit te-to-nt fa-bit position 1 one one s1 q1 2 zero zero zero zero 3 zero zero zero zero 4 zero zero zero zero 5 zero zero zero zero 6 one zero s2 q1 7 zero zero zero zero 8 zero zero zero zero 9 zero zero zero zero 10 zero zero zero zero 11 one zero s3 q3 12 zero zero zero zero 13 zero zero zero zero 14 zero zero zero zero 15 zero zero zero zero 16 one zero s4 q4 17 zero zero zero zero 18 zero zero zero zero 19 zero zero zero zero 20 zero zero zero zero 1 one one s1 q1 2 zero zero zero zero etc. terminal specific functions the mx97102 provides the following optional functions by setting bit tsf (stcr register) to 1. when termi- nal specific functions are activated (tsf=1), bit rss (cix0 register) is programmed for selecting watchdog function (rss=1) or external awake function (rss=0). deactivating the terminal specific functions is only pos- sible with a hardware reset. watchdog function (tsf=1, rss=1): during every time period of 128ms the processor has to program the wtc1 and wtc2 bits in the sequence, (wtc1, wtc2) = (1, 0) then (0, 1), to reset and restart the watchdog timer. otherwise, the timer expires and a wov interrupt (exir) together with a 125ms reset pulse is generated. external awake function a 16ms reset signal is generated by either a falling edge on the eaw line (subscriber awake) or a c/i code change (exchange awake). a corresponding interrupt status (saw or cisq) is also generated. moreover, it forces the idp1 line of the gci interface to zero. the consequence of this is that the gci interface and the mx97102 leaves the power-down state. 28 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 test functions the mx97102 provides several test and diagnostic func- tions which can be grouped ad follows: - digital loop via tlp (test loop, spcr register) com- mand bit: idp1 is internally connected with idp0, out- put from layer 1 (s/t) on idp0 is ignored; this is used for testing mx97102 functionality excluding layer 1; - test of layer-2 functions while disabling all layer-1 func- tions and pins associated with them (including clock- ing), via bits tem and pfs (test mode in adf1 regis- ter); the mx97102 is then fully compatible to the icc (siemens peb2070) seen at the iom2 interface. - loop at the analog end of the s interface; test loop 3 is activated with the c/i-channel command activate request loop (arl). an s interface is not re- quired since info3 is looped back to the receiver. when the receiver has synchronized itself to this signal, the message "test indication" ( or "awake test indication") is delivered in the c/i channel. in the test loop mode the s-interface awake detector is enabled i.e. if a level is detected (e.g. info2 /info4) this will be reported by the awake test indication (ati). the loop function is not effected by this condition and the internally generated 192 khz line clock does not de- pend on the signal received at the s interface. layer-2 functions for the isdn-basic access lapd, layer 2 of the d-channel protocol (ccitt i.441) includes functions for: - provision of one or more data link connections on a d channel (multiple lap). discrimination between the data link connections is performed by means of a data link connection identifier (dlci = sapi + tei). - hdlc framing - application of a balanced class of procedure in point- multipoint configuration. for the support of lapd the mx97102 contains an hdlc transceiver which is responsible for flag genera- tion/recognition, bit stuffing mechanism, crc check and address recognition. a powerful fifo structure with two 64-byte pools for transmit and receive directions and an intelligent fifo controller permit flexible transfer of protocol data units to and from the cpu system. the hdlc controller can be programmed to operate in various modes, which are different in the treatment of the hdlc frame in receive direction. thus, the receive data flow and the address recognition features can be programmed in a flexible way. in the auto mode the mx97102 handles elements of procedure of the lapd (s and i frames) according to ccitt i.441 fully autonomously. for the address rec- ognition the mx97102 contains four programmable reg- isters for individual sapi and tei values sap1-2 and tei1-2, plus two fixed values for "group" sapi and tei, sapg and teig. there are 5 different operating modes which can be set via the mode register. -auto-mode (mds2, mds1 = 00) characteristics: * full address recognition (1 or 2 bytes) * normal (mod 8) or extended (mod 128) con- trol field format * automatic processing of numbered frames of an hdlc procedure if a 2-byte address field is selected, the high address byte is compared with the fixed hex value fe or fc (group address) ad well ad with two individually pro- grammable values in sap1 and sap2 registers. ac- cording to the isdn lapd protocol, bit 1 of the high byte address will be interpreted as command/response bit (c/r) dependent on the setting of the cri bit in sap1, and will be excluded from the address comparison. simi- larly, the low address byte is compared with the fixed hex value ff (group tei) and two compare values pro- grammed in special registers (tei1, tei2). a valid ad- dress will be recognized in case the high and low byte of the address field match one of the compare values. the mx97102 can be called (addressed) with the fol- lowing address combination: * sap1/tei1 * sap1/ff (hex value) * sap2/ tei2 * sap2/ff (hex value) * fe or fc (hex value)/tei1 * fe or fc (hex value)/tei2 * fe or fc (hex value)/ff (hex value) 29 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 only the logical connection identified through the ad- dress combination sap1, tei1 will be processed in the auto mode, all others are handled as in the non-auto mode. the logical connection handled in the auto-mode must have a window size 1 between transmitted and acknowledged frames. hdlc frames with address fields that do not match with any of the address combina- tions, are ignored by the mx97102. in case of a 1-byte address, tei1 and tei2 will be used as compare regis- ters. according to the x.25 lapb protocol, the value in tei1 will be interpreted ad command and the value in tei2 as response. the control field is stored in the rhcr register and the i field in the rfifo. additional information is available in the rsta. - non-auto mode (mds2, mds1 = 01) characteristic: * full address recognition (1 or 2 bytes) * arbitrary window size all frames with valid addresses (address recognition identical to auto mode) are accepted and the bytes fol- lowing the address are transferred to the cpu via rhcr and rfifo. additional information is available in the rsta. - transparent mode 1 (mds2, mds1, mds0 = 101) characteristic: tei recognition a comparison is performed only on the second byte after the opening flag, with tei1, tei2 and group tei (ff hex value), and the rest of the frame in the rfifo. additional information is available in the rsta. - transparent mode 2 (mds2, mds1, mds0 = 110) characteristic: no address recognition every received frame is stored in the rfifo (first byte after opening flag to crc field). additional information is available in the rsta. - transparent mode 3 (mds2, mds1, mds0 = 111) characteristic: sapi recognition a comparison is performed on the first byte after the opening flag with sap1, sap2 and group sapi (fe/fc hex value). in the case of match, all the following bytes are stored in the rfifo. additional information is avail- able in the rsta. reception of frames a 2*32 byte fifo buffer (receive pools) is provided in the receive direction. the control of the data transfer between the cpu and the mx97102 is handled via in- terrupts. - rpf (receive pool full) interrupt, indicating that a 32-byte block of data can be read from the rfifo and the received message is not yet complete. - rme (receive message end) interrupt, indicating that the reception of one message is completed, i.e. either one message * 32 bytes or the last part of a message > 32bytes is stored in the rfifo. the organization of the rfifo is such that up to two short (* 32 bytes), successive messages, with all addi- tional information can be stored (see figure6-13). figure 6-10 contents of rfifo (short message) 0 31 rme receive message 1 (< 32 bytes) 0 31 rme receive message 2 (< 32 bytes) 30 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 note 1: only if a 2-byte address field is defined (mds0=1 in mode register). note 2: comparison with group tei is only made if a 2-byte address field is defined (mds0=1). note 3: in the case of an extended, modulo 128 control field format (mcs=1 in sap2 register) the control field is stored in the rhcr in compressed form (i frames). note 4: in the case of extended control field, only the first byte is stored in the rhcr, the second in the rfifo. depending on the message transfer mode the address and control fields of received frames are processed and stored in the receive fifo or in special registers as depicted in figure 6-11. figure 6-11 receive data flow flag address lligh sap1,sap2 fe, fc tei1, tei2 ff tei1, tei2 ff tei1, tei2 ff (note 1) (note 1) (note 2) (note 2) (note 3) (note 4) (note 4) address low control information crc flag auto-mode (u-and i-frames) non-auto mode transparent mode 3 symbol descriptions :checked automatically by mx97102 :compared with register or fixed value :stored information register or rfifo transparent mode 2 transparent mode 1 sap1,sap2 fe, fc sapr rfifo rfifo sap1,sap2 fe, fc rsta rfifo rhcr rhcr rhcr rfifo rfifo rsta rsta rsta rsta 31 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 when 32 bytes of a message longer than that are stored in the rfifo, the cpu is prompted to read out the data by an rpf interrupt. the cpu must handle this interrupt before more than 32 additional bytes are re- ceived, which would cause a "data overflow", this cor- responds to a maximum cpu reaction time of 16ms (data rate 16 kbit/s). after a remaining block of less than or equal to 16 bytes has been stored, it is possible to store the first 16 bytes of a new message (see figure6-12). the internal memory is now full. the arrival of additional bytes will result in "data overflow" (rsta: rdo) and a third new transmission of frames a 2*32 byte fifo buffer (transmit pools) is provided in the transmit direction. if the transmit pool is ready (which is true after an xpr interrupt or if the xfw bit in star is set), the cpu can write a data block of up to 32 bytes to the transmit fifo. after this, data transmis- sion can be initiated by command. message in "frame overflow" (exir: rfo). the gener- ated interrupts are inserted together with all additional information into a queue to be individually passed to the cpu. after an rpf or rme interrupt has been processed, i.e. the received data has been read from the rfifo, this must be explicitly acknowledged by the cpu issu- ing an rmc (receive message complete) command. the mx97102 can then release the associated fifo pool for new data. if there is an additional interrupt in the queue it will be generated after the rmc acknowledgement. two different frames types can be transmit- ted : transparent frame (command: xtf) or i frames (command: xif) as shown in fig- ure6-16. for transparent frames, the whole frame including address and control field must be written to the xfifo. figure 6-12 contents of the rfifo (long messages) 0 31 0 31 rpf rpf rfifo long message 0 31 0 15 16 31 rpf rme rme rfifo receive message 1 (< 48 bytes) message 2 (< 32 bytes) 32 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 figure 6-13 transmit data flow flag address control information symbol descriptions :generated automatically by mx97102 :written initially by cpu (info register) :loaded (repeatedly) by cpu upon mx97102 request (xpr interrupt) note: length of control field is 8 or 16 bit hdlc frame transmit i-frame (xif) auto mode, 8-bit addr. transmit i-frame (xif) auto mode, 16-bit addr. flag crc flag xad1 control flag crc flag xad1 xad2 control flag crc transmit transparent frame(xtf) all modes flag xfifo xfifo xfifo flag crc 33 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 if a 2-byte address field has been selected, the mx97102 takes the contents of the xad1 register to build the high byte of the address field, and the xad2 register to build to low byte of the address field. addi- tionally the c/r bit (bit 1of the high byte address, as defined by lapd protocol ) is set to "1" or "0" depen- dent on whether the frame is a command or a response. in the case of a 1 byte address, the mx97102 takes either the xad1 or xad2 register to differentiate be- tween command or response frame (as defined by x.25 lapb). the control field is also generated by the mx97102 in- cluding the receive and send sequence number and the poll/final (p/f) bit. for this purpose, the mx97102 internally manages send and receive sequence num- ber counters. in the auto-mode, s frames are sent autonomously by the mx97102. the transmission of u frames, however, must be done by the cpu. u frames must be sent as transparent frames (cmdr: xtf), i.e. address and con- trol field must be defined by the cpu. once the data transmission has been initiated by command (cmdr: xtf or xif), the data transfer between cpu and the mx97102 is controlled by interrupts. the mx97102 repeatedly requests another data packet or block by means of an ista:xpr interrupt, every time no more than 32 bytes are stored in the xfifo. the processor can then write further data to the xfifo and enable the continuation of frame transmission by issu- ing an xit/xtf command. if the data block which has been written last to the xfifo completes the current frame, this must be indicated additionally by setting the xme (transmit message end) command bit. the mx97102 then terminates the frame properly by ap- pending the crc and closing flag. if the cpu fails to respond to an xpr interrupt within the given reaction time, a data underrun condition oc- curs (xfifo holds no further valid data). in this case, the mx97102 automatically aborts the current frame by sending seven consecutive "ones" (abort se- quence). and the cpu is informed about this via an xdu (transmit data underrun) interrupt. it is also pos- sible to abort a message by software by issuing a cmdr:xres (transmitter reset) command, which causes an xpr interrupt. after an end of message indication from the cpu (cmdr: xme command), the termination of the trans- mission operation is indicated differently, depending on the selected message transfer mode and the transmit- ted frame type. if the mx97102 is operating in the auto mode, the win- dow size is limited to"1"; therefore an acknowledgement may be provided either by a received s or i frame with corresponding receive sequence number. if no acknowledgement is received within a certain time (pro- grammable), the mx97102 requests an acknowledgement by sending an s frame with the poll bit set (p=1) (rr or rnr). if no response is received again, this process is repeated in total n2 times (retry count, programmable via timr register). the termination of the transmission operation may be indicated either with: - xpr interrupt, if a positive acknowledgement has been received, - xmr interrupt, if a negative acknowledgement had been received, i.e. the transmitted message must be repeated (xmr = transmit message repeat), - tin interrupt, if no acknowledgement has been re- ceived at all after n2 times the expiration of the time period t1 (tin = timer interrupt, xpr interrupt is is- sued additionally). note: prerequisite for sending i frames in the auto-mode (xif) is that the internal operational mode of the timer has been selected in the mode register (tmd bit = 1). the transparent transmission of frames (xtf command) is possible in all message transfer mode. the success- ful termination of a transparent transmission is indicated by an xpr interrupt. in all cases, collisions which occur on the s-bus (d channel) before the first xfifo pool has been com- pletely transmitted and released are treated without cpu interaction. the mx97102 will retransmit the frame automatically. if a collision is detected after the first pool has been released, the mx97102 aborts the frame and requests the processor to repeat the frame with an xmr interrupt. 34 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 figure6-14 mx97102 interrupt structure interrupt structure and logic since the mx97102 provides only one interrupt request output (int), the cause of an interrupt is determined by the microprocessor by reading the interrupt status reg- ister (ista). in this register, seven interrupt sources can be directly read. the lsb of the ista points to eight non-critical interrupt sources which are indicated in the extend interrupt register (exir). figure6-16 shows the mx97102 interrupt structure. int rme rpf rsc xpr tin cisq sin exi mask rme rpf rsc xpr tin cisq sin exi ista mosr mocr mre1 mxe1 mre0 mxe0 sqxr ci1e sqie sqc sqrr cir1 cic1 cir0 bas c o d r 0 cic0 mdr1 mer1 mda1 mab1 mdr0 mer0 mda0 mab0 xmr xdu pce rfo sov mos saw wov exir 35 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 a read of the ista register clears all bits expect exi and cisq. cisq is cleared by reading cir0. a read of exir clears the exi bit in ista as well as the exir register. when all bits in ista are cleared, the interrupt line (pintn) in deactivated. each interrupt source in ista register can be selec- tively masked by setting to 1 the corresponding bit in mask. masked interrupt status bits are not indicated when ista is read. instead, they remain internally stored and pending, until the mask bit is reset to zero. read- ing the ista while a mask bit is active has no effect on the pending interrupt. in the event of an extended interrupt and of a c/i or s/ q channel change, exi and cisq are set even when the corresponding mask bits in mask are active, but no interrupt (int) is generated. except for cisq and mos all interrupt sources are directly determined by a read of ista and (possibly) exir. a cisq interrupt may originate from a change in the received s/q code (sqc), from a change in the re- ceived c/i channel 0 code (cic0) or form a change in the received c/i channel 1 code (cic1).these three corresponding status bits sqc, cic0 and cic1 are read then cleared in the cir0 register. sqc and cic1 can be individually disabled by clearing the enable bit sqie (sqxr register) or, respectively, ci1e (sqxr regis- ter). an interrupt status is indicated every time a valid new code is loaded in sqrr, cir0 or cir1. but in case of a code change, the new code is not loaded until the previous contents have been read. when this is done and a second code change has already occurred, a new interrupt is immediately generated and the new code replaces the previous one in the register. the code registers are buffered with a fifo size of two. thus, if several consecutive codes are detected, only the first and the last code is obtained at the first and second register read, respectively. the monitor data receive (mdr) and the moni- tor end of reception (mer) interrupt status bits have two enable bits, monitor receive interrupt enable (mre) and mr bit control (mrc). the monitor chan- nel data acknowledged (mda) and monitor chan- nel data abort (mab) interrupt status bits have a com- mon enable bit monitor interrupt enable (mxe). mre prevents the occurrence of the mdr status, in- cluding when the first byte of a packet is received, when mre is active (1) but mrc is inactive, the mdr-inter- rupt status is generated only for the first byte of a re- ceive packet. when both mre and mrc are active, mdr is generated and all received monitor bytes - marked by a 1-to-0 transition in mx bit - are stored. the int output is level active. it stays active until all interrupt sources have been serviced. if a new status bit is set while an interrupt serviced, the int line stays active. this may cause problem if the mx97102 is con- nected to edge-triggered interrupt controllers. to avoid these problems, it is recommended to mask all inter- rupts at the end of the interrupt service program and to enable the interrupts again. this is done by writing ff hex value to the mask register and to write back the old value of the mask register. 36 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 microprocessor interface connection single-chip microcontroller, such as 8048, 8031 or 8051, can meet the need of mx97102. mx97102 is built in various microprocessor interface, it fits perfectly into almost any 8-bit microprocessor system environment. the microprocessor interface can be selected to be ei- ther of the motorola type (with control signals cs, r/w, ds) of the siemens/intel non-multiplexed bus type (with control signals cs, wr, rd) or of the siemens/intel multiplexed address/data bus type (with wr, rd, ale). int(intx) rd wr ale (pscx) ad7....ad0 a15....a8 common bus a15-a0, d7-d0 memory figure 7: connecting the mx97102 to intel microcontroller 80c51 (80c188) mx97102 gci +5v s pintn prdn pwrn pale pcsn pad7....0 psx1 psx2 psr1 psr2 latch 37 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 s/t interface line transceiver functions for the s/t interface follows the electrical specifications of ccitti.430. according to this standard, pseudo-ternary encoding with 100% pulse width is used on the s/t interface. for both re- ceive and transmit direction, a 2:1 transformer is used to connect the mx97102 transceiver to the 4 wire s/t interface. the receiver is changed as a threshold detector with adaptively switched threshold levels. pin psr1 deliv- ers 2.5v as an output, which is the virtual ground of the input signal on pin psr2. e-channel monitoring this feature is provided by two ways, one way is to allow cpu to access two serial e-bits in a register, the other way is to get the e-bit signal from one pin of this chip. (please see application note pm0624 for details.) sdsx programming strobes 1 and 2 are provided, please see the applica- tion note for defails. ( * please see the application note, pm 0624) +5v vdd 2 : 1 psx1 psx2 psr1 psr2 mx97102 transmit pair protection circuits vssd vssa gnd 10uf figure 8: mx97102 external s-interface circuitry 2 : 1 receive pair 38 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 internal register table 8 : hdlc operation and status registers addr. name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 description (hex) 00-1f fifo r/w tx/rx fifo address 20 ista r rme rpf rsc xpr tin cisq sin exi interrupt status register 20 mask w rme rpf rsc xpr tin cisq sin exi mask register 21 star r xdov xfw xrnr rrnr mbr mac1 x mac0 status register 21 cmdr w rmc rres rnr sti xtf xif xme xres command register 22 mode r/w mds2 mds1 mds0 tmd rac dim2 dim1 dim0 mode register 23 timr r/w cnt cnt cnt v a l u e timer register 24 exir r xmr xdu pce rfo sov mos saw wov extended interrupt register 24 xad1 w transmit address 1 25 rbcl r rbc7 rbc6 rbc5 rbc4 rbc3 rbc2 rbc1 rbc0 receive frame byte count low 25 xad2 w transmit address 2 26 sapr r received sapi 26 sap1 w sapi1 sapi1 sapi1 sapi1 sapi1 sapi1 cri 0 individual sapi 1 27 rsta r rda rdo crc rab sa1 sa0 c/r ta receive status register 27 sap2 w sapi2 sapi2 sapi2 sapi2 sapi2 sapi2 mcs 0 individual sapi 2 28 tei1 w tei1 tei1 tei1 tei1 tei1 tei1 tei1 ea individual tei 1 29 rhcr r receive hdlc control 29 tei2 w tei2 tei2 tei2 tei2 tei2 tei2 tei2 ea individual tei 2 2a rbch r xac vn1 vn0 ov rbc11 rbc10 rbc9 rbc8 receive fram byte count high 2b star2 r 0 0 0 0 wfa mult trec sdet status register 2 2b star2 w 0 0 0 0 0 mult 0 0 status register 2 39 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 table 9 : special purpose registers addr. name r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 description (hex) 30 spcr r/w spu 0 0 tlp c1c1 c1c0 c2c1 c2c0 ser ial port control reg. 31 cir0 r sqc bas codr0 codr0 codr0 codr0 cic0 cic1 command/indication receive 0 31 cix0 w rss bac codx0 codx0 codx0 codx0 1 1 command/indication transmit 0 32 mor0 r monitor receive 0 32 mox0 w monitor transmit 0 33 cir1 r codr1 codr1 codr1 codr1 codr1 codr1 mr1 mx1 command/indication receive 1 33 cix1 w codx1 codx1 codx1 codx1 codx1 codx1 1 1 command/indication transmit 1 34 mor1 r monitor receive 1 34 mox1 w monitor transmit 1 35 c1r r/w channel register 1 36 c2r r/w channel register 2 37 b1cr r b1-channel register 37 stcr w tsf tba2 tba1 tba0 st1 st0 sc1 sc0 sync transfer control register 38 b2cr r b2-channel register 38 adf1 w wtc1 wtc2 tem pfs iof 0 0 itf additional feature reg.1 39 adf2 r/w ims 0 0 0 ods d1c2 d1c1 d1c0 additional feature reg.2 3a mosr r mdr1 mer1 mda1 mab1 mdr0 mer0 mda0 mab0 monitor status reg. 3a mocr w mre1 mrc1 mxe1 mxc1 mre0 mrc0 mxe0 mxc0 monitor control reg. 3b sqrr r idc cfs ci1e syn sqr1 sqr2 sqr3 sqr4 s-,q-channel receive register 3b sqxr w idc cfs ci1e sqie sqx1 sqx2 sqx3 sqx4 s-,q-channel transmit register 3c adf3 r/w 0 0 0 1 stm1 stm0 max1 max0 additional feature reg.3 3d emr r 0 0 0 0 0 0 emr1 emr0 e-channel bits reg. 3d edr w 0 0 0 0 d_sizer0 d_sflags d_unarb emon d/e channel control reg. 3e adf4 r/w ims 0 0 0 bfwd d2c2 d2c1 d2c0 b-e xchang, sds2 reg. ordering information part no. package mx97102qc 44 pin plcc MX97102UC 64 pin lqfp 40 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 revision history rev. no. description page date 1.1 preliminary release july/28/1997 1.2 change editing nov/1997 add ordering information and revision history change words in drawings add "not used" pins in pin descriptions 1.3 page6, table 3 changed nov/1997 1.4 wording errors apr/14/1998 1.5 change feature description may/21/1998 1.6 storage temperature range " -65 c to 125 c" replaced by "-55 c to 150 c" p4 jun./15/1998 1.7 add 64-pin package a ug/21/1998 1.8 made for cd-rom release sep/15/1998 1.9 modify 64-pin package outline data oct/20/1998 2.0 64 pin p-lqfp package information content changed p16 oct/27/1998 2.1 new revision adds e-channel monitoring function, extra sds2 pin p1,3,4, apr/01/1999 2.2 add one e-bit pin p10~35 dec/17/1999 add lqfp pin description revise figure 8 add lqfp package data add more descriptions 2.3 add pre-filter compensation p22 jan/21/2000 2.4 contents modify p5,8 apr/28/2000 2.5 modify state diagram 6-9(a)&6-9(b) p23,24 sep/05/2000 41 p/n:pm0473 rev. 2.5, sep. 05, 2000 mx97102 package information 44-pin plastic leaded chip carrier (plcc) item millimeters inches a 17.53 . 12 .699 . 005 b 16.59 . 12 .653 . 12 c 16.59 . 12 .653 . 12 d 17.53 . 12 .690 . 12 e 1.95 .077 f 4.70 max. .185 max. g 2.55 . 25 .100 . 010 h .51 min. .020 min. i 1.27 [typ.] .050 [typ.] j .71 . 10 .028 . 004 k .46 . 10 .018 . 004 l 15.50 . 51 .610 . 020 m .53 r .025 r n .25 [typ.] .010 [typ.] note: each lead centerline is located within .25 mm[.01 inch] of its true position [tp] at maximum material condition. item millimeters inches a 16 .63 b 14 .55 c 14 .55 d 16 .63 e 12 [typ.] .47 [typ.] f 1 [typ.] .039 [typ.] g 1 [typ.] .039 [typ.] h .35 . 05 .014 . 002 i 0.8 .031 j 1 .039 k .6 . 15 .024 . 006 l .15 . 05 .006 . 002 m 1.4 . 05 .057 . 002 n .1 . 05 .004 . 002 o 1.6 [max.] .063 [max.] note: each lead centerline is located within .25 mm[.01 inch] of its true position [tp] at maximum material condition. 64-pin plastic low-profile quad flat package (p-lqfp) f g h i k j m n e l cd b a 640 44 1 13 7 17 18 28 23 33 39 29 a b e cd ih g f m k l j n o m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. 42 mx97102 |
Price & Availability of MX97102UC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |